"VV Square"building, Plot.No.TS 710/1b1 & 2B1, CMC Ward No 18, Moka road, Gandhinagar, Ballari-583 101. 583101 Bellari IN
Kendriya Vidyalaya Ballari
"VV Square"building, Plot.No.TS 710/1b1 & 2B1, CMC Ward No 18, Moka road, Gandhinagar, Ballari-583 101. Bellari, IN
+918050151380 https://www.trendypaper.com/s/5b1a00c581a9afd8ff765190/ms.settings/5256837ccc4abf1d39000001/5b928defbda50e15d4c76434-480x480.png" [email protected]
9789350388921- 5bbefed666988c11012f0a1c VLSI Design (Anna University) https://www.trendypaper.com/s/5b1a00c581a9afd8ff765190/ms.products/5bbefed666988c11012f0a1c/images/5c7e4013f5946a4deb463d9a/5c7e4016f5946a4deb463da8/5c7e4016f5946a4deb463da8.jpg UNIT - I CMOS Technology (Chapter - 1) A brief history-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non-ideal I-V effects, DC transfer characteristics - CMOS technologies, Layout design rules, CMOS process enhancements, Technology related CAD issues, Manufacturing issues. UNIT - II Circuit Characterization and Simulation (Chapter - 2) Delay estimation, Logical effort and transistor sizing, Power dissipation, Interconnect, Design margin, Reliability, Scaling - SPICE tutorial, Device models, Device characterization, Circuit characterization, Interconnect simulation. UNIT - III Combinational and Sequential Circuit Design (Chapter - 3) Circuit families - Low power logic design - Comparison of circuit families - Sequencing static circuits, Circuit design of latches and flip flops, Static sequencing element methodology - Sequencing dynamic circuits - Synchronizers. UNIT - IV CMOS Testing (Chapter - 4) Need for testing - Testers, Taxt fixtures and test programs - Logic verification - Silicon debug principles - Manufacturing test - Design for testability - Boundary scan. UNIT - V Specification using Verilog HDL (Chapter - 5) Basic concepts - Identifiers - Gate primitives, Gate delays, Operators, Timing controls, Procedural assignments conditional statements, Data flow and RTL, Structural gate level switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches, structural gate level description of decoder, Equality detector, Compatator, Priority encoder, Half adder, Full adder, Ripple carry adder, D latch and D flip-flop. 9789350388921-
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UNIT - I CMOS Technology (Chapter - 1) A brief history-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non-ideal I-V effects, DC transfer characteristics - CMOS technologies, Layout design rules, CMOS process enhancements, Technology related CAD issues, Manufacturing issues. UNIT - II Circuit Characterization and Simulation (Chapter - 2) Delay estimation, Logical effort and transistor sizing, Power dissipation, Interconnect, Design margin, Reliability, Scaling - SPICE tutorial, Device models, Device characterization, Circuit characterization, Interconnect simulation. UNIT - III Combinational and Sequential Circuit Design (Chapter - 3) Circuit families - Low power logic design - Comparison of circuit families - Sequencing static circuits, Circuit design of latches and flip flops, Static sequencing element methodology - Sequencing dynamic circuits - Synchronizers. UNIT - IV CMOS Testing (Chapter - 4) Need for testing - Testers, Taxt fixtures and test programs - Logic verification - Silicon debug principles - Manufacturing test - Design for testability - Boundary scan. UNIT - V Specification using Verilog HDL (Chapter - 5) Basic concepts - Identifiers - Gate primitives, Gate delays, Operators, Timing controls, Procedural assignments conditional statements, Data flow and RTL, Structural gate level switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches, structural gate level description of decoder, Equality detector, Compatator, Priority encoder, Half adder, Full adder, Ripple carry adder, D latch and D flip-flop.

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